TestSimpleLed.vhd
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-- Company:
-- Engineer:
--
-- Create Date: 06.10.2015 21:46:50
-- Design Name:
-- Module Name: TestSimpleLed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestSimpleLed is
-- Port ( );
end TestSimpleLed;
architecture Behavioral of TestSimpleLed is
component SimpleLed
port (
Button : in std_logic;
Led : out std_logic
);
end component;
--Inputs
signal Button : std_logic := '0'; -- Signal is high active
--Outputs
signal Led : std_logic;
--Test
signal TestCase : natural;
signal TestErr : std_logic := '0';
begin
uut: SimpleLed port map (
Button => Button,
Led => Led
);
stim_proc: process
begin
wait for 100 ns;
report "=======================================================";
report "Only end of test and errors will be reported";
TestCase <= 1;
wait for 100 ns;
if (Led /= '0') then
TestErr <= '1';
report "Initial state failed";
end if;
TestCase <= 2;
Button <= '1';
wait for 100 ns;
if (Led /= '1') then
TestErr <= '1';
report "Button pressed, but LED is off";
end if;
TestCase <= 3;
Button <= '0';
wait for 100 ns;
if (Led /= '0') then
TestErr <= '1';
report "Button released, but LED is on";
end if;
TestCase <= 0;
wait for 100 ns;
TestErr <= not TestErr;
wait for 30 ns;
TestErr <= not TestErr;
wait for 100 ns;
if (TestErr = '0') then
report "Test completed successfully";
else
report "Test completed with error(s)";
end if;
report "=======================================================";
assert false; -- stop simulation
wait;
end process;
end Behavioral;