TestSysService.vhd

-------------------------------------------------------------------------------
-- Copyright (c) 2017 by Stefan Milch.	All rights reserved.
-------------------------------------------------------------------------------
--! @file		 TestSysService.vhd
--! @brief		 Test shell for module SysService. \n
--!
-------------------------------------------------------------------------------
library ieee;
	use ieee.std_logic_1164.all;
	use std.textio.all;

entity TestSysService is
	generic (
		BoardIdx : integer	:= 0 -- 0: ZYBO, 1: ARTY
	);
end TestSysService;

architecture behavior of TestSysService is

	-- Component Declaration for the Unit Under Test (UUT)
	component SysService
		port (
			ExtClk		: in  std_logic; --! External clock
			Clk 		: out std_logic; --! Processing clock
			Reset		: in  std_logic; --! High acitve asynchronous reset input
			Init		: out std_logic; --! High acitve synchronous reset output
			TimeBase	: out std_logic_vector(8 downto 0); --! CE for 1 Hz .. 100 MHz
			TimeStamp	: out std_logic_vector(54 downto 0) --! Timestamp (> 10 years @ 100 MHz)
		);
	end component;

	-- Time definitions
	type	 tCycle is array(0 to 1) of time;
	constant cycleTimes 	: tCycle := (0 => 8 ns, 1 => 10 ns);
	constant Clk_period 	: time	:= cycleTimes(BoardIdx); -- clock period of selected board

	--Inputs
	signal Ext_Clk		: std_logic := '0';
	signal Reset		: std_logic := '0';

	--Outputs
	signal Clk			: std_logic;
	signal Init 		: std_logic;
	signal TimeBase 	: std_logic_vector(8 downto 0);
	signal TimeStamp	: std_logic_vector(54 downto 0);

	--Test
	file report_file	: text;
	signal TestCase 	: integer;
	signal TestErr		: std_logic := '0';

	--! print to output file
	procedure tb_report(constant report_text : in string) is
		variable line_out: line;
	begin
		write(line_out,report_text);
		writeline(report_file, line_out);
	end tb_report;

	--! wait a number of cycles
	procedure WaitCycles(constant cycles : in integer) is
		variable i : integer;
	begin
		for i in 1 to cycles loop
			wait until rising_edge(Ext_Clk);
		end loop;
	end WaitCycles;

begin
	-- Instantiate the Unit Under Test (UUT)
	uut: SysService
		port map (
			ExtClk		=> Ext_Clk,
			Clk 		=> Clk,
			Reset		=> Reset,
			Init		=> Init,
			TimeBase	=> TimeBase,
			TimeStamp	=> TimeStamp
		);

	--! Generate system clock
	p_clk : process
	begin
		Ext_Clk <= not Ext_Clk;
		wait for Clk_period/2;
	end process;

	--! Check for test bench time out
	p_control : process
	begin
		wait for 20 ms;
		-- the test bench should already have terminated!
		assert false
		report "Test timed out!"
		severity failure;
	end process;

	-- Stimulus process
	stim_proc: process
		variable expected_time : time;
	begin
		-- prepare reporting
		file_open(report_file,"../../../TestSysService.log",WRITE_MODE);
		tb_report("Testing SysService:");
		tb_report("====================");

		TestCase <= 1;

		TestCase <= 0;
		WaitCycles(1);
		TestErr <= not TestErr;
		WaitCycles(1);
		TestErr <= not TestErr;
		WaitCycles(500);
		if (TestErr = '0') then
			tb_report("Test completed successfully");
		else
			tb_report("Test completed with error(s)");
		end if;
		file_close(report_file);
		assert false
		report "Test terminated. This is not a failiure!"
		severity failure;
		wait;
	end process;

end;