SysService.vhd

-------------------------------------------------------------------------------
-- Copyright (c) 2017 by Stefan Milch.	All rights reserved.
-------------------------------------------------------------------------------
--! @file		 SysService.vhd
--! @brief		 FPGA reset and time handling \n
--!
-------------------------------------------------------------------------------
library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	use ieee.std_logic_unsigned.all ;

--! FPGA reset and time handling
entity SysService is
	port (
		ExtClk		: in  std_logic; --! External clock
		Clk 		: out std_logic; --! Processing clock
		Reset		: in  std_logic; --! High acitve asynchronous reset input
		Init		: out std_logic; --! High acitve synchronous reset output
		TimeBase	: out std_logic_vector(8 downto 0); --! CE for 1 Hz .. 100 MHz
		TimeStamp	: out std_logic_vector(54 downto 0) --! Timestamp (> 10 years @ 100 MHz)
	);
end SysService;

--! FPGA reset and time handling
architecture RTL of SysService is

-- ============================================================================
-- constant declarations
-- ===================
constant TimeIdx10ns	   	: integer := 0;
constant TimeIdx100ns	   	: integer := 1;
constant TimeIdx1us 	   	: integer := 2;
constant TimeIdx10us	   	: integer := 3;
constant TimeIdx100us	   	: integer := 4;
constant TimeIdx1ms 	   	: integer := 5;
constant TimeIdx10ms	   	: integer := 6;
constant TimeIdx100ms 	   	: integer := 7;
constant TimeIdx1s		   	: integer := 8;

-- ============================================================================
-- signal declarations
-- ===================

-- Clock and reset
signal ProcClk			: std_logic;					--! Internal processing clock
signal GenInitR 		: std_logic := '1'; 			--! Causes an init pulse after power on
signal ResetR			: std_logic;					--! Synchronized reset input
signal InitC			: std_logic;					--! Synchronous reset condition
signal InitR			: std_logic;					--! Synchronous reset

-- Time stamp

-- Time base

begin

	-- Clock generation
	ProcClk 	<= ExtClk;
	Clk 		<= ProcClk;

	--! Reset generation
	p_reset : process (ProcClk)
	begin
		if rising_edge(ProcClk) then
			GenInitR	<= GenInitR and not InitR;	-- Release InitR after it was activated
			InitR		<= InitC;
			ResetR		<= Reset;
		end if;
	end process;

	InitC				<=	ResetR or GenInitR; 		-- Reset on button and power on
	Init				<=	InitR;

	--! Time base
	p_timebase : process (ProcClk)
	begin
		if rising_edge(ProcClk) then
			if (InitR = '1') then
			else
			end if;
		end if;
	end process;

end RTL;