SimpleState.vhd

-------------------------------------------------------------------------------
-- Copyright (c) 2017 by Stefan Milch.	All rights reserved.
-------------------------------------------------------------------------------
--! @file		 SimpleState.vhd
--! @brief		 Control PWM by simple state machine \n
--!
-------------------------------------------------------------------------------
library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	use ieee.std_logic_unsigned.all ;

--! Control PWM by simple state machine
entity SimpleState is
	generic (
		BoardIdx	: integer  := 0; -- 0: ZYBO, 1: ARTY
		Simulation	: boolean  := false
	);
	port (
		EXT_CLK 	: in  std_logic; --! 125 MHz system clock
		BTN 		: in  std_logic_vector(3 downto 0); --! Button inputs, high acitve
		LED 		: out std_logic_vector(3 downto 0) --! LED outputs, high acitve
	);
end SimpleState;

--! Control PWM by simple state machine
architecture RTL of SimpleState is

-- ============================================================================
-- component declarations
-- ===================
component SysService
	port (
		ExtClk		: in  std_logic; --! external clock
		Clk 		: out std_logic; --! processing clock
		Reset		: in  std_logic; --! High acitve asynchronous reset input
		Init		: out std_logic; --! High acitve synchronous reset output
		TimeBase	: out std_logic_vector(8 downto 0); --! CE for 1 Hz .. 100 MHz
		TimeStamp	: out std_logic_vector(54 downto 0) --! Timestamp (> 10 years @ 100 MHz)
	);
end component;

-- ============================================================================
-- constant declarations
-- ===================
type	 tCycle is array(0 to 1) of time;
constant cycleTimes 	: tCycle := (0 => 8 ns, 1 => 10 ns);
constant cycleTime		: time	:= cycleTimes(BoardIdx);

-- ============================================================================
-- signal declarations
-- ===================

-- system services
signal Clk				: std_logic;					--! Internal processing clock
signal Init 			: std_logic;					--! Synchronous reset
signal TimeBase 		: std_logic_vector(8 downto 0); --! CE for 1 Hz .. 100 MHz
signal TimeStamp		: std_logic_vector(54 downto 0);	--! Timestamp

-- input and output
signal ButtonR			: std_logic_vector(3 downto 0); --! Button inputs after input flipflops
signal LedC 			: std_logic_vector(3 downto 0); --! LED output control
signal LedR 			: std_logic_vector(3 downto 0); --! LED output register

-- button functions
signal Button1R 		: std_logic_vector(3 downto 0); --! Delayed button signals for edge detection
signal ButtonPressC 	: std_logic_vector(3 downto 0); --! Button was pressed

begin

	 --! Input-Stage
	p_in : process (Clk)
	begin
		if rising_edge(Clk) then
			ButtonR 	<= BTN;  -- input FF for Button signals
			Button1R	<= ButtonR; -- Delayed button inputs
		end if;
	end process;

	ButtonPressC		<=	ButtonR and not Button1R;	-- rising edge detection of buttons

	 --! Output-Stage
	p_out : process (Clk)
	begin
		if rising_edge(Clk) then
			if (Init = '1') then
				LedR		<= (others => '0');
				LED 		<= (others => '0'); 
			else
				LedR		<= LedC;
				LED 		<= LedR;
			end if;
		end if;
	end process;

	-- system services
	i_sys_service : SysService
		port map (
			ExtClk		=> EXT_CLK,
			Clk 		=> Clk,
			Reset		=> BTN(0),
			Init		=> Init,
			TimeBase	=> TimeBase,
			TimeStamp	=> TimeStamp
		);

end RTL;