BlinnkingLed.vhd

-------------------------------------------------------------------------------
-- Copyright (c) 2016 by Stefan Milch.  All rights reserved.
-------------------------------------------------------------------------------
--! @file        BlinkingLed.vhd
--! @brief       Toggle a LED controled by a buttons \n
--!
-------------------------------------------------------------------------------
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all ;

--! Toggle a LED controled by a buttons
entity BlinkingLed is
    port (
        EXT_CLK     : in  std_logic; --! 125 MHz system clock
        BTN         : in  std_logic_vector(3 downto 0); --! Button inputs, high acitve
        LED         : out std_logic --! LED output, high acitve
    );
end BlinkingLed;

--! Toggle a LED controled by a buttons
architecture RTL of BlinkingLed is

-- ============================================================================
-- signal declarations
-- ===================

-- reset
signal GenInitR         : std_logic := '1';             --! Causes an init pulse after power on
signal InitC            : std_logic;                    --! Synchronous reset condition
signal InitR            : std_logic;                    --! Synchronous reset

-- input and output
signal Clk              : std_logic;                    --! Internal processing clock

-- temporary
signal EnableC          : std_logic;                    --! Example for a clock enable

begin

-- clock generation
    Clk     <= EXT_CLK;

    --! Simple flipflops
    p_simple : process (Clk)
    begin
        if rising_edge(Clk) then
            GenInitR    <= GenInitR and not InitR;  -- Release InitR after it was activated
            InitR       <= InitC;
        end if;
    end process;

    InitC               <=  GenInitR;               -- Reset on power on

    --! Flipflops with synchronous reset
    p_sync : process (Clk)
    begin
        if rising_edge(Clk) then
            if (InitR = '1') then
            else
            end if;
        end if;
    end process;
    
    --! Flipflops with synchronous reset and clock enable
    p_ce : process (Clk)
    begin
        if rising_edge(Clk) then
            if (InitR = '1') then
            elsif (EnableC = '1') then
            end if;
        end if;
    end process;
    
end RTL;